Introducing probability in Colorwave

Technical Repor

Probabilistic DCS: An RFID reader-to-reader anti-collision protocol

The wide adoption of radio frequency identification (RFID) for applications requiring a large number of tags and readers makes critical the reader-to-reader collision problem. Various anti-collision protocols have been proposed, but the majority require considerable additional resources and costs. Distributed color system (DCS) is a state-of-the-art protocol based on time division, without noteworthy additional requirements. This paper presents the probabilistic DCS (PDCS) reader-to-reader anti-collision protocol which employs probabilistic collision resolution. Differently from previous time division protocols, PDCS allows multichannel transmissions, according to international RFID regulations. A theoretical analysis is provided in order to clearly identify the behavior of the additional parameter representing the probability. The proposed protocol maintains the features of DCS, achieving more efficiency. Theoretical analysis demonstrates that the number of reader-to-reader collisions after a slot change is decreased by over 30%. The simulation analysis validates the theoretical results, and shows that PDCS reaches better performance than state-of-the-art reader-to-reader anti-collision protocol

Evaluation Criteria for Reader-to-Reader Anti-collision Protocols

Technical Repor

Banknote identification through unique fluorescent properties

The use of printed banknotes is widespread despite cashless payment methods: for example, more than 27 billion euro banknotes are currently in circulation, and this amount is constantly increasing. Unfortunately, many false banknotes are in circulation, too. Central banks worlwide are continuously striving to reduce the counterfeiting. To fight against the criminal practice, a range of security features are added to banknotes, such as watermarks, micro-printing, holograms, and embossed characters. Beside these well-known characteristics, the colored fibers inside every banknote have strong potential as a security feature, but have so far been poorly exploited. The mere presence of colored fibers does not guarantee the banknote genuineness, as they can be drawn or printed by counterfeiters. However, their random position can be exploited to uniquely identify the banknote. This paper presents a technique for automatically recognizing fibers and efficiently storing their positions, considering realistic application scenarios. The classification accuracy and fault tolerance of the proposed method are theoretically demonstrated, thus showing its applicability regardless of banknote wear or any implementation issue. This is a major advantage with respect to state-of-the-art anti-counterfeit approaches. The proposed security method is strictly topical, as the European Central Bank plans to redesign euro banknotes by 2024

Personal Assistance and Monitoring Devices Applications

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Investigation of interference models for RFID systems

The reader-to-reader collision in an RFID system is a challenging problem for communications technology. In order to model the interference between RFID readers, different interference models have been proposed, mainly based on two approaches: single and additive interference. The former only considers the interference from one reader within a certain range, whereas the latter takes into account the sum of all of the simultaneous interferences in order to emulate a more realistic behavior. Although the difference between the two approaches has been theoretically analyzed in previous research, their effects on the estimated performance of the reader-to-reader anti-collision protocols have not yet been investigated. In this paper, the influence of the interference model on the anti-collision protocols is studied by simulating a representative state-of-the-art protocol. The results presented in this paper highlight that the use of additive models, although more computationally intensive, is mandatory to improve the performance of anti-collision protocols

A Review on Fall Prediction and Prevention System for Personal Devices: Evaluation and Experimental Results

Injuries due to unintentional falls cause high social cost in which several systems have been developed to reduce them. Recently, two trends can be recognized. Firstly, the market is dominated by fall detection systems, which activate an alarm after a fall occurrence, but the focus is moving towards predicting and preventing a fall, as it is the most promising approach to avoid a fall injury. Secondly, personal devices, such as smartphones, are being exploited for implementing fall systems, because they are commonly carried by the user most of the day. This paper reviews various fall prediction and prevention systems, with a particular interest to the ones that can rely on the sensors embedded in a smartphone, i.e., accelerometer and gyroscope. Kinematic features obtained from the data collected from accelerometer and gyroscope have been evaluated in combination with different machine learning algorithms. An experimental analysis compares the evaluated approaches by evaluating their accuracy and ability to predict and prevent a fall. Results show that tilt features in combination with a decision tree algorithm present the best performance

Analysis and optimization of synchronization algorithms for multicore architectures

Multicore design is a major issue in modern computer architectures. Programmers are urged to design innovative algorithms by exploiting multicore facilities. Since synchronization affects the performance of multithread algorithms, the selection of an effective synchronization mechanism is critical for multicore environments. Modern computers provide special hardware instructions that allow to atomically read and modify the content of a word (e.g., the cmpxchg instruction in Intel x86 CPUs), so they can be used for synchronization of threads. Moreover, software techniques can synchronize threads without any dependency on hardware instructions. This study considers the main synchronization techniques, such as Ticket lock, which guarantees fairness execution to all threads, Filter lock, which is intended for multiple threads, Readers-writer lock, which aims to solve the readers-writers problem and Read-Copy Update (RCU), which reduces the overhead in readers-writer lock. The first contribution of this study is to evaluate the costs of the mentioned synchronization techniques, due for example to memory access, system call, and spinning, i.e., the act of querying (or in some cases modifying) an object in memory and waiting for its content. In order to reduce the costs of the mentioned synchronization mechanisms, state-of-the-art approaches exploit hardware or software techniques. The second contribution of this study is the analysis of both hardware and software solutions to reduce the synchronization costs. Moreover, a comparative study to highlight benefits and drawbacks of the different synchronization mechanisms has been performed. Different software solutions such as backoff, a waiting time to reduce the bus traffic, non blocking algorithm, a synchronization mechanism without blocking primitives, and compiler barrier, a compiler directive to avoid reordering of the instructions, are well-known techniques which are investigated in this study. Beside software solutions, hardware manufacturers introduce various facilities in shared memory or distributed environment to enhance the performance of synchronization mechanisms. Examples of hardware solutions are hardware message passing and different layer of caches in the shared memory environment, and Remote Direct Memory Access (RDMA) in distributed environment. Experimental benchmarks have been executed on a node of cluster (Opteron 6276 2.3 GHz CPU with 16 cores and running CentOS 6.3 Operating System2). The experiments, which are intended to represent a useful aid for researchers and practitioners interested in optimization of parallel algorithms, show that: 1. The update rate directly impacts on performance, even if a non blocking algorithm is exploited. 2. The cost of keeping data locality should not exceed the cost of cache misses. 3. Exploiting a non blocking synchronization algorithm (i.e., RCU) leads to a better performance. 4. Critical section length should be reduced as much as possible in order to increase the performance. 5. In order to reduce the bus traffic, it is better to avoid spinning. 6. Hardware message passing can increase the performance of shared memory synchronization model. 7. Synchronization methods with heavy instructions should be avoided

Analysis and optimization of synchronization algorithms for multicore architectures

Multicore design is a major issue in modern computer architectures. Programmers are urged to design innovative algorithms by exploiting multicore facilities. Since synchronization affects the performance of multithread algorithms, the selection of an effective synchronization mechanism is critical for multicore environments. Modern computers provide special hardware instructions that allow to atomically read and modify the content of a word (e.g., the cmpxchg instruction in Intel x86 CPUs), so they can be used for synchronization of threads. Moreover, software techniques can synchronize threads without any dependency on hardware instructions. This study considers the main synchronization techniques, such as Ticket lock, which guarantees fairness execution to all threads, Filter lock, which is intended for multiple threads, Readers-writer lock, which aims to solve the readers-writers problem and Read-Copy Update (RCU), which reduces the overhead in readers-writer lock. The first contribution of this study is to evaluate the costs of the mentioned synchronization techniques, due for example to memory access, system call, and spinning, i.e., the act of querying (or in some cases modifying) an object in memory and waiting for its content. In order to reduce the costs of the mentioned synchronization mechanisms, state-of-the-art approaches exploit hardware or software techniques. The second contribution of this study is the analysis of both hardware and software solutions to reduce the synchronization costs. Moreover, a comparative study to highlight benefits and drawbacks of the different synchronization mechanisms has been performed. Different software solutions such as backoff, a waiting time to reduce the bus traffic, non blocking algorithm, a synchronization mechanism without blocking primitives, and compiler barrier, a compiler directive to avoid reordering of the instructions, are well-known techniques which are investigated in this study. Beside software solutions, hardware manufacturers introduce various facilities in shared memory or distributed environment to enhance the performance of synchronization mechanisms. Examples of hardware solutions are hardware message passing and different layer of caches in the shared memory environment, and Remote Direct Memory Access (RDMA) in distributed environment. Experimental benchmarks have been executed on a node of cluster (Opteron 6276 2.3 GHz CPU with 16 cores and running CentOS 6.3 Operating System2). The experiments, which are intended to represent a useful aid for researchers and practitioners interested in optimization of parallel algorithms, show that: 1. The update rate directly impacts on performance, even if a non blocking algorithm is exploited. 2. The cost of keeping data locality should not exceed the cost of cache misses. 3. Exploiting a non blocking synchronization algorithm (i.e., RCU) leads to a better performance. 4. Critical section length should be reduced as much as possible in order to increase the performance. 5. In order to reduce the bus traffic, it is better to avoid spinning. 6. Hardware message passing can increase the performance of shared memory synchronization model. 7. Synchronization methods with heavy instructions should be avoided

Nonlinear predictive threshold model for real-time abnormal gait detection

Falls are critical events for human health due to the associated risk of physical and psychological injuries. Several fall related systems have been developed in order to reduce injuries. Among them, fall-risk prediction systems are one of the most promising approaches, as they strive to predict a fall before its occurrence. A category of fall-risk prediction systems evaluates balance and muscle strength through some clinical functional assessment tests, while other prediction systems investigate the recognition of abnormal gait patterns to predict a fall in real-time. The main contribution of this paper is a nonlinear model of user gait in combination with a threshold-based classification in order to recognize abnormal gait patterns with low complexity and high accuracy. In addition, a dataset with realistic parameters is prepared to simulate abnormal walks and to evaluate fall prediction methods. The accelerometer and gyroscope sensors available in a smartphone have been exploited to create the dataset. The proposed approach has been implemented and compared with the state-of-the-art approaches showing that it is able to predict an abnormal walk with a higher accuracy (93.5%) and a higher efficiency (up to 3.5 faster) than other feasible approaches